(1) Field of the Invention
This invention relates to integrated circuit semiconductor devices, and more particularly to a method for fabricating dynamic random access memory (DRAM) devices having one or more Gigabits of memory cells. This novel method improves the memory-cell density using auto self-aligning techniques while reducing electrical shorts between the word lines and polysilicon plug contacts. The method also reduces capacitor node leakage currents, and parasitic capacitance. Also reduced are the electrical shorts between the closely spaced polysilicon plugs via keyholes (voids) in the interpolysilicon oxide (IPO) due to poor gap filling with the IPO.
(2) Description of the Prior Art
As integrated circuit density increases, it becomes increasing difficult to manufacture ultra large scale integrated (ULSI) circuits because of process limitations. This problem is particularly acute for making future DRAM devices having more than a Gigabit of memory cells. These process limitations are best understood by referring to the conventional DRAM structure in the prior art FIGS. 1A and 1B. FIG. 1A shows a portion of a partially completed DRAM cell. Typically a shallow trench isolation (STI) 12 is formed in a silicon substrate 10 surrounding and electrically isolating device (memory cell) areas. A barrier layer 13, such as silicon nitride (Si.sub.3 N.sub.4), is deposited and patterned to form openings over the device areas and a gate oxide 14 is grown on the substrate 10 for field effect transistors (FETs). A doped polysilicon layer 16, a refractory metal silicide layer 18 and an insulating cap layer 20 are deposited and patterned to form word lines (layers 16, 18) over the STI 12 while concurrently forming FET gate electrodes over the thin gate oxide 14. Doped source/drain areas 17(N) are formed adjacent to the gate electrodes by ion implantation and a conformal insulating layer is deposited and anisotropically plasma etched back to form sidewall spacers 22 on the sidewalls of the FET gate electrodes (patterned layers 16 and 18). Next an insulating layer 24 is deposited and polished back to form the first interpolysilicon oxide layer (IPO-1) and a photoresist mask and plasma etching are used to etch contact openings that extend over the FET gate electrodes (self-aligned) and down to the source/drain areas. One problem encountered in this conventional self-align process is damage to the source/drain areas 17 when the contact holes are plasma etched. Another problem is the overetching of the cap oxide layer 20, as depicted at point B in FIG. 1A, which can result in shorts to the FET gate electrodes when the contact holes are filled with a doped polysilicon 26 (poly plugs) to make electrical contacts. Also the poly plugs also overlap the gate electrodes resulting in increased parasitic capacitance, resulting in an increased RC time constants and reduced circuit speed. Another problem encountered is poor gap filling between the closely spaced word lines (patterned layers 16, 18 & 20) having high aspect ratios, as depicted at point A in FIG. 1A. When closely spaced contact openings 2 are etched in the insulating layer 24 and into the voids A between the word lines shorts can occur when the contact holes 2 are filled with polysilicon 26 to form the poly plugs. A major shortcoming of the conventional process is the need to align the contact hole extending over the FET gate electrodes, and requires relaxing the alignment rules which makes it difficult to achieve the required density for Gigabit DRAM chips. Still another problem with the conventional process is depicted in FIG. 1B for concurrently making borderless contacts 4 to the silicon substrate, that is, contacts that extend over the shallow trench isolation (STI). When contact openings 2 are etched in the insulating layer 24, it is necessary to use an etch stop layer 13 (Si.sub.3 N.sub.4) to prevent over etching the STI at the edge and damaging the contact. However, this requires additional process steps.
Numerous methods of making DRAM devices with improved electrical characteristics while increasing memory cell density have been reported. One method is described by Huang in U.S. Pat. No. 5,783,462 in which external contacts for testing stacked capacitor DRAM, but does not address the above problem. Another method for making DRAM devices with increased density and improved sign-to-noise ratio is described by Keeth in U.S. Pat. No. 5,864,181 but also does not address the above concerns. Cherng in U.S. Pat. No. 5,837,577 teaches a method for making DRAM capacitor node contacts self-aligned to. the bit lines but also does not address the above problems.
However, there is still a need in the industry to provide an improved process with novel cell design that is applicable to DRAMs having more than a Gigabit of memory cells. Further while reducing the narrow spacings for Gigabit DRAMS by minimizing the alignment tolerance ground rule, it is also necessary to reduce parasitic capacitance, capacitor node leakage currents, and electrical shorts between closely spaced polysilicon plug contacts to achieve an acceptable circuit performance and an acceptable product yield.